1. Field Of The Invention
The present invention relates to a logarithmic amplifying circuit and, more particularly, to a logarithmic amplifying circuit suited for a MOS integrated circuit.
2. Description Of The Related Arts
A conventional logarithmic amplifying circuit of the type is generally realized in a bipolar integrated circuit. A logarithmic amplifying circuit realized in a MOS integrated circuit is disclosed in, e.g., Japanese Patent Laid-Open No. 62-292010.
The logarithmic amplifying circuit in this MOS integrated circuit is designed in such a manner that multistage MOS differential amplifiers are connected in cascade, and squaring full-wave rectifiers are respectively connected to an input of the first stage and output terminals of the subsequent stages. With this arrangement, signals at these input and output terminals are subjected to squaring full-wave rectification, and the outputs from the squaring full-wave rectifiers are added together. For this reason, these outputs are affected by the characteristics of the respective squaring full-wave rectifiers, which include dynamic range characteristics, and hence excellent logarithmic characteristics cannot be obtained.